1. [1] E. Dubrova, “Multiple-valued logic in VLSI: Challenges and opportunities,” Proc. NORCHIP'99, pp.340-349, Nov. 1999.
2. [2] R. Ho, W. Mai, and M.A. Horowitz, “The future of wires,” Proc. IEEE, vol.89, no.4, pp.490-504, April 2001.
3. [3] S.L. Hurst, “Multiple-valued logic, its status and its future,” IEEE Trans. Comput., vol.C-33, no.2, pp.1160-1179, Dec. 1984.
4. [4] C.J. Fang, C.H. Huang, J.S. Wang, and C.W. Yeh, “Fast and compact dynamic ripple carry adder design,” Proc. IEEE Asia-Pacific Conf. ASIC, pp.25-28, 2002.
5. [5] R. Martel, T. Schmidt, H.R. Shea, T. Hertel, and P. Avouris, “Single- and multi-wall carbon nanotube field-effect transistors,” Appl. Phys. Lett., vol.73, no.17, pp.2447-2449, Oct. 1998.