Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications-Reference-Cited by-同舟云学术

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications

Published:2012 Issue:7 Volume:E95.D Page:1858-1871
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

LIU Bo¹,CAO Peng¹,ZHU Min²,YANG Jun¹,LIU Leibo²,WEI Shaojun²,SHI Longxing¹

Affiliation:

1. National ASIC system Engineering Research Center, Southeast University

2. Institute of Microelectronics, Tsinghua University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E95.D/7/E95.D_1858/_pdf

Reference24 articles.

1. [1] T. Cervero, S. López, G.M. Callicó, F. Tobajas, V. de Armas, J. López, and R. Sarmiento, “Survey of reconfigurable architectures for multimedia applications,” VLSI Circuits and Systems IV (Proceedings Volume), SPIE Microtechnologies for the New Millennium, Dresden, Germany, 2009, doi: 10.1117/12.821713.

2. [2] J. V. T. of ITU-T, “Draft itu-t recommendation and final draft international standard of joint video specification (itu-t rec. h.264 iso/iec 14496-10 avc),” Document JVT-GO50, Dec. 2003.

3. Overview of the H.264/AVC video coding standard

4. [4] A. Joch, F. Kossentini, H. Schwarz, T. Wiegand, and G.J. Sullivan, “Performance comparison of video coding standards using Lagrangian coder control,” Image Processing. 2002. Proceedings. 2002 International Conference on, pp.II-501-II-504, vol.2, 2002.

5. [5] M. Zhu, L. Liu, S. Yin, C. Yin, and S. Wei, “A cycle-accurate simulator for a reconfigurable multi-media system,” IEICE Trans. Inf. & Syst., vol.E93-D, no.12, pp.3202-3210, Dec. 2010.

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