Affiliation:
1. Kyushu Institute of Technology
2. Advanced Micro Devices, Inc.
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software
Reference26 articles.
1. [1] L.-T. Wang, C.-W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann Publishers Inc., San Francisco, CA, USA, July 2006. 10.1016/B978-0-12-370597-6.X5000-8
2. [2] J. Saxena, K.M. Butler, V.B. Jayaram, S. Kundu, N.V. Arvind, P. Sreeprakash, and M. Hachinger, “A case study of IR-Drop in structured at-speed testing,” Proc. IEEE Int'l Test Conf., pp.1098-1104, Sept. 2003. 10.1109/TEST.2003.1271098
3. [3] T. Yoshida and M. Watari, “MD-SCAN method for low power scan testing,” Proc. IEEE Asian Test Symp., pp.80-85, Nov. 2002. 10.1109/ATS.2002.1181690
4. [4] R. Wang, B. Bhaskaran, K. Natarajan, A. Abdollahian, K. Narayanun, K. Chakrabarty, and A. Sanghani, “A programmable method for low-power scan shift in SoC integrated circuits,” Proc. IEEE VLSI Test Symp., April 2016. 10.1109/VTS.2016.7477289
5. [5] P. Girard, N. Nicolici, and X. Wen, eds., Power-Aware Testing and Test Strategies for Low Power Devices, Springer, Oct. 2010. 10.1007/978-1-4419-0928-2
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