A high voltage half bridge gate driver with mismatch-insensitive dead-time generator

Author:

Cho Kunhee1,Lee Sungpah1,Kwon Duckki1

Affiliation:

1. Power Conversion Korea, Fairchild Semiconductor

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference7 articles.

1. [1] B. Murari, F. Bertotti, and G. A. Vignola, Smart Power ICs, Springer, New York, 2002.

2. [2] Y. Yin and R. Zane, “Dual Low-Voltage IC Design for High-Voltage Floating Gate Drives,” IEEE Trans. Circuits Syst. I, vol. 55, no. 6, pp. 1751-1758, June 2008.

3. [3] J. A. A. Qahouq, H. Mao, H. J. Al-Atrash, and I. Batarseh, “Maximum efficiency point tracking (MEPT) method and digital dead time control implementation,” IEEE Trans. Power Electron., vol. 21, no. 5, pp. 1273-1281, Sept. 2006.

4. [4] Fairchild Semiconductor, “FAN7393A Datasheet,” Accessed Dec. 2010, [Online] http://www.fairchildsemi.com/ds/FA/FAN7393A.pdf

5. [5] National Semiconductor, “LM5105 Datasheet,” Accessed May 2011, [Online] http://www.national.com/ds/LM/LM5105.pdf

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