Panzer: A 6 × 6 photonic router for optical network on chip
Author:
Affiliation:
1. State Key Laboratory of Integrated Service Networks, Xidian University
2. School of Computer Science and Technology, Xidian University
3. School of Institute of Microelectronics, Xidian University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/13/21/13_13.20160719/_pdf
Reference10 articles.
1. [1] A. D. A. Cisseet al.: “A Fully Optical Ring Network-on-Chip with Static and Dynamic Wavelength Allocation,” IEICE Trans. Inf. Syst. E96.D (2013) 2545 (DOI: 10.1587/transinf.E96.D.2545).
2. [2] J. H. Leeet al.: “System-Level Design Framework for Insertion-Loss-Minimized Optical Network-on-Chip Router Architectures,” J. Lightwave Technol. 32 (2014) 3161 (DOI: 10.1109/JLT.2014.2336234).
3. [3] J. C. Pichelet al.: “Sparse matrix–vector multiplication on the Single-Chip Cloud Computer many-core processor,” J. Parallel Distrib. Comput. 73 (2013) 1539 (DOI: 10.1016/j.jpdc.2013.07.017).
4. [4] Y. Xieet al.: “Crosstalk noise analysis and optimization in 5 × 5 hitless silicon-based optical router for optical networks-on-chip (ONoC),” J. Lightwave Technol. 30 (2012) 198 (DOI: 10.1109/JLT.2011.2178396).
5. [5] A. W. Poonet al.: “Cascaded microresonator-based matrix switch for silicon on-chip optical interconnection,” Proc. IEEE 97 (2009) 1216 (DOI: 10.1109/JPROC.2009.2014884).
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