A Single Amplifier-Based 12-bit 100MS/s 1V 19mW 0.13.MU.m CMOS ADC with Various Power and Area Minimized Circuit Techniques-Reference-Cited by-同舟云学术

A Single Amplifier-Based 12-bit 100MS/s 1V 19mW 0.13.MU.m CMOS ADC with Various Power and Area Minimized Circuit Techniques

Published:2011 Issue:8 Volume:E94-C Page:1282-1288
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

KOO Byeong-Woo¹,PARK Seung-Jae¹,AHN Gil-Cho¹,LEE Seung-Hoon¹

Affiliation:

1. Department of Electronic Engineering, Sogang University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/transele/E94.C/8/E94.C_8_1282/_pdf

Reference20 articles.

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2. [2] Y.J. Kim, K.H. Lee, M.H. Lee, and S.H. Lee, “A 0.31pJ/conversion-step 12-bit 100MS/s 0.13µm CMOS A/D converter for 3G communication systems,” IEICE Trans. Electron., vol.E92-C, no.9, pp.1194-1200, Sept. 2009.

3. [3] T. Ito, D. Kurose, T. Yamaii, and T. Itakura, “55mW 1.2V 12-bit 100-MSps pipelined ADCs for wireless receivers,” European Solid-State Circuits Conference, pp.540-543, Sept. 2006.

4. [4] T.N. Andersen, A. Briskemyr, F. Telsto, J. Bjornsen, T.E. Bonnerud, B. Hernes, and O. Moldsvor, “A 97mW 110MS/s 12b pipeline ADC implemented in 0.18µm digital CMOS,” Proc. Design, Automation and Test in Europe, pp.219-222, March 2005.

5. [5] H.C. Choi, Y.J. Kim, S.W. Lee, J.Y. Han, O.B. Kwon, Y.L. Kim, and S.H. Lee, “A 52mW 0.56mm² 1.2V 12b 120MS/s SHA-free dual-channel Nyquist ADC based on mid-code calibration,” Proc. ISCAS, pp.9-12, May 2008.

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