An FPGA Implementation of the Two-Dimensional FDTD Method and Its Performance Comparison with GPGPU
Author:
Affiliation:
1. Tokyo University of Agriculture and Technology
2. NTT Microsystem Integration Laboratories
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/transele/E97.C/7/E97.C_697/_pdf
Reference23 articles.
1. [1] R. N. Schneider, L. E. Turner, and M. M. Okoniewski, “Application of FPGA technology to accelerate the finite-difference time-domain (FDTD) method,” Proceedings of the 2002 ACM/SIGDA tenth international symposium on field-programmable gate arrays, FPGA '02, New York, NY, USA, pp. 97–105, ACM, Feb. 2002.
2. [2] J. Nickolls, I. Buck, M. Garland, and K. Skadron, “Scalable parallel programming with CUDA,” Queue, vol. 6, no. 2, pp. 40–53, Mar./Apr. 2008.
3. [3] J. P. Durbano, F. E. Ortiz, J. R. Humphrey, M. S. Mirotznik, and D. W. Prather, “Hardware implementation of a three-dimensional finite-difference time-domain algorithm,” Antennas and Wireless Propagation Letters, IEEE, vol. 2, no. 1, pp. 54–57, 2003.
4. [4] W. Chen, P. Kosmas, M. Leeser, and C. Rappaport, “An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm,” Proceedings of the 2004 ACM/SIGDA 12th international symposium on field programmable gate arrays, FPGA '04, New York, NY, USA, pp. 213–222, ACM, 2004.
5. [5] S. Endo, J. Sonoda, and M. Sato, “Acceleration of FDTD method with time and space pipeline in FPGA implementation,” The Transactions of the Institute of Electronics, Information and Communication Engineers. B, vol. 92, no. 1, pp. 243–249, Jan. 2009. (in Japanese).
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