A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs-Reference-Cited by-同舟云学术

A High Output Resistance 1.2-V VDD Current Mirror with Deep Submicron Vertical MOSFETs

Published:2014 Issue:5 Volume:E97.C Page:423-430
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

TANOI Satoru¹²,ENDOH Tetsuo¹²³

Affiliation:

1. Graduate School of Engineering, Tohoku University

2. JST-CREST

3. Center for Innovative Integrated Electronic Systems, Tohoku University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E97.C/5/E97.C_423/_pdf

Reference17 articles.

1. [1] B. Razavi, Design of Analog CMOS Integrated Circuits, pp.135-145, McGraw-Hill, New York, 2001.

2. [2] Y. Tsividis and C. McAndrew, Operation and Modeling of the MOS Transistor, pp.253-258, Oxford, New York, 2011.

3. [3] E. Säckinger and W. Guggenbühl, “A high swing, high impedance MOS cascode circuit,” IEEE J. Solid-State Circuits, vol.25, pp.289-298, Feb. 1990.

4. [4] T. Itakura and Z. Czarnul, “High output-resistance CMOS current mirrors for low-voltage applications,” IEICE Trans. Fundamentals, vol.E80-A, no.1, pp.230-232, Jan. 1997.

5. [5] S. Tanoi and T. Endoh, “A low voltage operated current mirror for analog designs with deep submicron vertical MOSFETs,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Korea, Technical Digest, 6A-1, pp.233-237, June 2013.

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Loss analysis and optimum design of a highly efficient and compact CMOS DC–DC converter with novel transistor layout using 60 nm multipillar-type vertical body channel MOSFET;Japanese Journal of Applied Physics;2018-03-16