A Schmitt Trigger Based SRAM with Vertical MOSFET-Reference-Cited by-同舟云学术

A Schmitt Trigger Based SRAM with Vertical MOSFET

Published:2012 Issue:5 Volume:E95.C Page:792-801
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

NA Hyoungjun¹,ENDOH Tetsuo¹

Affiliation:

1. Center for Interdisciplinary Research, Tohoku University, JST-CREST

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E95.C/5/E95.C_5_792/_pdf

Reference13 articles.

1. [1] N. Yoshinobu, H. Masahi, K. Takayuki, and K. Itoh, “Review and future prospects of low-voltage RAM circuits,” IBM J. Res. Dev., vol.47, pp.525-552, 2003.

2. [2] L. Chang, D. Fried, J. Hergenrother, J. Sleight, R. Dennard, R.R. Montoye, L. Sekaric, S. McNab, W. Topol, C. Adams, K. Guarini, and W. Haensch, “Stable SRAM cell design for the 32nm node and beyond,” in Symp. VLSI Technology Dig., pp.128-129, 2005.

3. A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

4. [5] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, Prentice Hall, NJ, 2002.

5. [6] H. Takato, K. Sunouchi, N. Okabe, A. Nitayama, K. Hieda, F. Horiguchi, and F. Masuoka, “High performance CMOS surrounding gate transistor (SGT) for ultra high density LSI's,” IEDM Tech. Dig., pp.222-225, Dec. 1988.

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