Implementation of a radix-2k fixed-point pipeline FFT processor with optimized word length scheme
Author:
Affiliation:
1. School of Information and Communication Engineering, Communication University of China
2. Huawei Hisilicon
3. Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/16/13/16_16.20190181/_pdf
Reference31 articles.
1. [1] S. Li, et al.: “A 128/256-point pipeline FFT/IFFT processor for MIMO OFDM system IEEE 802.16e,” Proc. IEEE Int. Symp. Circuits Syst. (2010) 1488 (DOI: 10.1109/ISCAS.2010.5537355).
2. [2] S. He and M. Torkelson, “Designing pipeline FFT processor for OFDM (de)modulation,” 29 (1998) 257 (DOI: 10.1109/ISSSE.1998.738077).
3. [3] Y.-W. Lin and C.-V. Lee: “Design of an FFT/IFFT processor for MIMO OFDM systems,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. 54 (2007) 807 (DOI: 10.1109/TCSI.2006.888664).
4. [4] F.-L. Yuan, et al.: “A 256-point dataflow scheduling 2 × 2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN,” (2008) 309 (DOI: 10.1109/ASSCC.2008.4708789).
5. [5] Y.-W. Lin, et al.: “A dynamic scaling FFT processor for DVB-T applications,” IEEE J. Solid-State Circuits 39 (2004) 2005 (DOI: 10.1109/JSSC.2004.835815).
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