Power and thermal management in SRAM and DRAM using adaptive body biasing technique-Reference-Cited by-同舟云学术

Power and thermal management in SRAM and DRAM using adaptive body biasing technique

Published:2019 Issue:19 Volume:16 Page:20190432-20190432
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

HamaAli Goran¹,Sulaiman Diary¹²,Ibrahim Muhammed¹

Affiliation:

1. Electrical Engineering Department, Engineering College, Salahaddin University-Erbil

2. College of Engineering and Computer Science, Lebanese-French University (LFU)

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/16/19/16_16.20190432/_pdf

Reference30 articles.

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2. [2] K. Chandrasekar: “High-level power estimation and optimization of DRAMs,” PhD Thesis, Delft University of Technology (2014).

3. [3] X. Yang, et al.: “A priority-based selective bit dropping strategy to reduce DRAM and SRAM power in image processing,” IEICE Electron. Express 13 (2016) 20160990 (DOI: 10.1587/elex.13.20160990).

4. [4] E. N. Shauly: “CMOS leakage and power reduction in transistors and circuits: Process and layout considerations,” J. Low Power Electron. Appl. 2 (2012) 1 (DOI: 10.3390/jlpea2010001).

5. [5] H. H. Shin and E.-Y. Chung: “In-DRAM cache management for low latency and low power 3D-stacked DRAMs,” Micromachines 10 (2019) 124 (DOI: 10.3390/mi10020124).