A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links-Reference-Cited by-同舟云学术

A 0.8–3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links

Published:2019 Issue:19 Volume:16 Page:20190505-20190505
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Hwang Heejae¹,Kim Jongsun¹

Affiliation:

1. School of Electronic and Electrical Engineering, Hongik University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/16/19/16_16.20190505/_pdf

Reference30 articles.

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2. [2] H.-K. Jung, et al.: “A 4.35 Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications,” Symp. on VLSI Circuits (2015) 184 (DOI: 10.1109/VLSIC.2015.7231255).

3. [3] R. Inti, et al.: “A digital-intensive 2-to-9.2 Gb/s/pin memory controller I/O with fast-response LDO in 10 nm CMOS,” Symp. on VLSI Circuits (2018) 151 (DOI: 10.1109/VLSIC.2018.8502323).

4. [4] S.-M. Lee, et al.: “A 0.6 V 4.266 Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller,” ISSCC (2017) 398 (DOI: 10.1109/ISSCC.2017.7870429).

5. [5] H.-W. Lee, et al.: “A 1.35 V 5.0 Gb/s/pin GDDR5M with 5.4 mW standby power and an error-adaptive duty-cycle corrector,” ISSCC (2014) 434 (DOI: 10.1109/ISSCC.2014.6757502).