High-performance approximate half and full adder cells using NAND logic gate

Author:

Waris Haroon1,Wang Chenghua1,Liu Weiqiang1

Affiliation:

1. College of Electronic and Information Engineering, Nanjing University of Aeronautics and Astronautics

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference30 articles.

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2. [2] R. Nair: “Big data needs approximate computing: Technical perspective,” Commun. ACM 58 (2014) 104 (DOI: 10.1145/2688072).

3. [3] S. Venkataramani, et al.: “Computing approximately, and efficiently,” DATE (2015) 748 (DOI: 10.7873/DATE.2015.1113).

4. [4] V. K. Chippa, et al.: “Analysis and characterization of inherent application resilience for approximate computing,” DAC (2013) 113 (DOI: 10.1145/2463209.2488873).

5. [5] J. Schlachter, et al.: “Design and applications of approximate circuits by gate-level pruning,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25 (2017) 1694 (DOI: 10.1109/TVLSI.2017.2657799).

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