Novel bit-serial semi-systolic array structure for simultaneously computing field multiplication and squaring
Author:
Affiliation:
1. Depatment of Computer Engineering, College of Computer Engineering and Sciences, Prince Sattam Bin Abdulaziz University
2. Microelectronics Department, Electronics Research Institute
3. ECE Department, University of Victoria
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/16/23/16_16.20190600/_pdf
Reference30 articles.
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2. [2] W. T. Huang, et al.: “Concurrent error detection and correction in a polynomial basis multiplier over gf(2m),” IET Inf. Secur. 4 (2010) 111 (DOI: 10.1049/iet-ifs.2009.0160).
3. [3] K.-W. Kim and J.-C. Jeon: “Polynomial basis multiplier using cellular systolic architecture,” IETE J. Res. 60 (2014) 194 (DOI: 10.1080/03772063.2014.914699).
4. [4] K. W. Kim and J. C. Jeon: “A semi-systolic montgomery multiplier over gf(2m),” IEICE Electron. Express 12 (2015) 20150769 (DOI: 10.1587/elex.12.20150769).
5. [5] K. J. Lee and K. Y. Yoo: “Linear systolic multiplier/squarer for fast exponentiation,” Inf. Process. Lett. 76 (2000) 105 (DOI: 10.1016/S0020-0190(00)00131-9).
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