Cooperative communication based barrier synchronization in on-chip mesh architectures-Reference-Cited by-同舟云学术

Cooperative communication based barrier synchronization in on-chip mesh architectures

Published:2011 Issue:22 Volume:8 Page:1856-1862
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Chen Xiaowen¹²,Lu Zhonghai²,Jantsch Axel²,Chen Shuming¹,Liu Hai¹

Affiliation:

1. National University of Defense Technology

2. KTH - Royal Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/8/22/8_22_1856/_pdf

Reference10 articles.

1. [1] J. Hennessy and D. Patterson, Computer Architecture: A Quantitative Approach, 4th Edition, Morgan Kaufmann Publishers, 2007.

2. [2] T. Hoefler, et al., “A Survey of Barrier Algorithms for Coarse Grained Supercomputers,” Chemnitzer Informatik Berichte, vol. 4, no. 3, Dec. 2004.

3. [3] B. Wilkinson, Parallel Programming: Techniques and Applications Using Networked Workstations and Parallel Computers, Prentice Hall, 2004.

4. [4] O. Villa, et al., “Efficiency and Scalability of Barrier Synchronization on NoC Based Many-core Architectures,” Proc. Int'l Conf. on Compilers, Architectures and Synthesis for Embedded Systems (CASES'08), pp. 81-89, 2008.

5. Algorithms for scalable synchronization on shared-memory multiprocessors

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