The sprint process of Al interconnects with low-temperature PVD via filling-Reference-Cited by-同舟云学术

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The sprint process of Al interconnects with low-temperature PVD via filling

Published:2004 Issue:9 Volume:1 Page:263-268
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Yoda Takashi¹,Ezawa Hirokazu¹,Tsutsumi Kaori¹,Honda Makoto¹

Affiliation:

1. Advanced ULSI Process Engineering Department, Process & Manufacturing Engineering Center, Toshiba Corporation Semiconductor Company

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/1/9/1_9_263/_pdf

Reference4 articles.

1. Temperature dependence of the Al-fill processes for submicron-via structures

2. [3] J. Wada, Y. Oikawa, T. Katata, N. Nakamura, and M. B. Anand, “Low Resistance Dual Damascene Process by New Al Reflow using Nb Liner, ” 1998 Symp. VLSI Technology. Dig, pp. 48-49, 1998.

3. [4] M. Morita, M. Honda, H. Ezawa, T. Yoda, K. Goto, A. Sakuma, and M. Aruga, “CVD/PVD Al Filling Process with Ti/TiN Liner for Dual Damascene Interconnections, ” Advanced Metallization Conference 1998 (MRS, Warrendale, PA), pp. 427-432, 1998.

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