An Automatic Method of Mapping I/O Sequences of Chip Execution onto High-level Design for Post-Silicon Debugging
Author:
Affiliation:
1. Department of Electrical Engineering and Information Systems, The University of Tokyo
2. VLSI Design and Education Center, The University of Tokyo
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
http://www.jstage.jst.go.jp/article/transfun/E94.A/7/E94.A_7_1519/_pdf
Reference17 articles.
1. [1] AMBA interface specifications: http://www.arm.com/products/system-ip/amba/
2. [2] M. Abramovici, P. Bradley, K.r Dwarakanath, P. Levin, G. Memmi, and D. Miller, “A reconfigurable design-for-debug infrastructure for SoCs,” Proc. Design Automation Conference, pp.7-12, 2006.
3. [3] N. Bombieri, N. Deganello, and F. Fummi, “Integrating RTL IPs into TLM designs through automatic transactor generation,” Proc. Design, Automation and Test in Europe, pp.15-20, 2008.
4. [4] Collett ASIC/IC Verification Study, 2004 (data for 180nm and 130nm).
5. Interprocedural slicing using dependence graphs
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