Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher-Reference-Cited by-同舟云学术

Compact Architecture for ASIC and FPGA Implementation of the KASUMI Block Cipher

Published:2011 Issue:12 Volume:E94-A Page:2628-2638
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

YAMAMOTO Dai¹,ITOH Kouichi¹,YAJIMA Jun¹

Affiliation:

1. FUJITSU LABORATORIES LTD.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E94.A/12/E94.A_12_2628/_pdf

Reference30 articles.

1. A survey on sensor networks

2. [2] K. Finkenzeller, RFID Handbook, Fundamentals and Applications in Contactless Smart Cards and Identification Second Edition, John Wiley & Sons, 2003.

3. [3] Third Generation Partnership Project, 3GPP TS 35.202 v7.0.0 Document 2: KASUMI Specification, June 2007.

4. New block encryption algorithm MISTY

5. [5] ISO/IEC18033-3, “Information technology — Security techniques — Encryption algorithms — Part 3: Block ciphers,” July 2005.

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