1. [1] N. Tega, H. Miki, F. Pagette, D. Frank, A. Ray, M. Rooks, W. Haensch, and K. Torii, “Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20nm,” Proc. Symp. VLSI Technol., pp.50-51, June 2009.
2. [2] N. Tega, H. Miki, M. Yamaoka, H. Kume, T. Mine, T. Ishida, Y. Mori, R. Yamada, and K. Torii, “Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM,” Proc. IEEE Int. Rel. Physics Symp., pp.541-546, April 2008.
3. [3] N. Tega, H. Miki, T. Osabe, A. Kotabe, K. Otsuga, H. Kurata, S. Kamohara, K. Tokami, Y. Ikeda, and R. Yamada, “Anomalously large threshold voltage fluctuation by complex random telegraph signal in floating gate flash memory,” Proc. IEEE Int. Electron Devices Meeting, pp.1-4, Dec. 2006.
4. [4] K. Takeuchi, T. Nagumo, S. Yokogawa, K. Imai, and Y. Hayashi, “Single-charge-based modeling of transistor characteristics fluctuations based on statistical measurement of RTN amplitude,” Proc. Symp. VLSI Technol., pp.54-55, June 2009.
5. [5] K. Ito, T. Matsumoto, S. Nishizawa, H. Sunagawa, K. Kobayashi, and H. Onodera, “Modeling of random telegraph noise under circuit operation | simulation and measurement of RTN-induced delay fluctuation,” Proc. IEEE Int. Symp. Quality Electronic Design, pp.1-6, March 2011.