Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips-Reference-Cited by-同舟云学术

Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips

Published:2009 Issue:12 Volume:E92-A Page:3007-3015
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

FU Qiang¹,LUK Wai-Shing¹,TAO Jun¹,ZENG Xuan¹,CAI Wei²

Affiliation:

1. State Key Lab. of ASIC & System, MOE Key Lab. for Computational Physical Sciences, Fudan University

2. Department of Mathematics, University of North Carolina at Charlotte

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E92.A/12/E92.A_12_3007/_pdf

Reference15 articles.

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3. Statistical timing analysis under spatial correlations

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5. [5] S. Bhardwaj, S. Vrudhula, P. Ghanta, and Y. Cao, “Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits, ” Design Automation Conference, pp.791-796, July 2006.