Affiliation:
1. Graduate School of Fundamental Science and Engineering, Waseda University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Reference20 articles.
1. [1] S. Tajima, N. Togawa, M. Yanagisawa, and Y. Shi, “C-element based soft-error hardened latch designs,” The 30th workshop on circuits and systems, pp.214-219, May 2017 (in Japanese).
2. [2] C. Chang, H. Huang, Y. Lin, and C. Wen, “SERL: Soft error resilient latch design,” Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp.1-4, April 2016. 10.1109/vlsi-dat.2016.7482555
3. [3] P. Shivakumar, M. Kistler, S.W. Keckler, D. Burger, and L. Alvis, “Modeling the effect of technology trends on the soft error rate of combinational logic,” Proc. Dependable Systems and Networks, pp.389-398, 2002. 10.1109/dsn.2002.1028924
4. [4] A. Yan, H. Liang, Z. Huang, and C. Jiang, “High-performance, low-cost, and highly reliable radiation hardened latch design,” Electron. Lett., vol.52, no.2, pp.139-141, Jan. 2016. 10.1049/el.2015.3020
5. [5] H.R. Zarandi, S.G. Miremadi, C. Argyrides, and D.K. Pradhan, “Fast SEU detection and correction in LUT configuration bits of SRAM-based FPGAs,” Proc. International Parallel and Distributed Processing Symposium, pp.1-6, 2007. 10.1109/ipdps.2007.370378
Cited by
5 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献