An FPGA-Based Information Detection Hardware System Employing Multi-Match Content Addressable Memory

Author:

LE Duc-Hung1,INOUE Katsumi2,SOWA Masahiro1,PHAM Cong-Kha1

Affiliation:

1. University of Electro-Communications

2. Advanced Original Technoligies Inc.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Architectural analysis of 1-D to 2-D array conversion of priority encoder;International Journal of System Assurance Engineering and Management;2023-07-04

2. Architectural Improvement and Performance Evaluation of 1D-to-2D Array Conversion Priority Encoder;2022 International Conference on Smart Generation Computing, Communication and Networking (SMART GENCON);2022-12-23

3. A 0.9-V 50-MHz 256-bit 1D-to-2D-based single/multi-match priority encoder with 0.67-nW standby power on 65-nm SOTB CMOS;Microprocessors and Microsystems;2020-03

4. Architectural design tradeoffs in SRAM-based TCAMs;IEICE Electronics Express;2019

5. A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS;2018 IEEE International Symposium on Circuits and Systems (ISCAS);2018

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