Area-Efficient LUT-Like Programmable Logic Using Atom Switch and Its Delay-Optimal Mapping Algorithm
Author:
Affiliation:
1. Graduate School of Information Science and Engineering, Ritsumeikan University
2. Department of Computer Science, College of Information Science and Engineering, Ritsumeikan University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E100.A/7/E100.A_1418/_pdf
Reference12 articles.
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2. [2] M. Miyamura, S. Nakaya, M. Tada, T. Sakamoto, K. Okamoto, N. Banno, S. Ishida, K. Ito, H. Hada, N. Sakimura, T. Sugibayashi, and M. Motomura, “Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS,” IEEE International Solid-State Circuits Conference (ISSCC) Dig. Tech. Papers, pp.228-229, 2011. 10.1109/isscc.2011.5746296
3. [3] M. Miyamura, M. Tada, T. Sakamoto, N. Banno, K. Okamoto, N. Iguchi, and H. Hada, “First demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch,” IEEE International Electron Devices Meeting (IEDM) Dig. Tech. Papers, pp.10.6.1-10.6.4, 2012. 10.1109/iedm.2012.6479020
4. [4] J. Luu, J. Goeders, M. Wainberg, A. Somerville, T. Yu, K. Nasartschuk, M. Nasr, S. Wang, T. Liu, N. Ahmed, K.B. Kent, J. Anderson, J. Rose, and V. Betz, “VTR 7.0: Next generation architecture and CAD system for FPGAs,” ACM Trans. Reconfigurable Technol. Syst., vol.7, no.2, pp.6:1-6:30, June 2014. 10.1145/2617593
5. [5] P. Jamieson, K.B. Kent, F. Gharibian, and L. Shannon, “Odin II-an open-source verilog HDL synthesis tool for CAD research,” Proc. 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), pp.149-156, 2010. 10.1109/fccm.2010.31
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