Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement-Reference-Cited by-同舟云学术

Post-Routing Double-Via Insertion for X-Architecture Clock Tree Yield Improvement

Published:2011 Issue:2 Volume:E94-A Page:706-716
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

TSAI Chia-Chun¹,KUO Chung-Chieh²,LEE Trong-Yen²

Affiliation:

1. Department of Computer Science and Information Engineering, Nanhua University

2. Graduate Institute of Computer and Communication, National Taipei University of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

http://www.jstage.jst.go.jp/article/transfun/E94.A/2/E94.A_2_706/_pdf

Reference21 articles.

1. [1] L.K. Scheffer, “Physical cad changes to incorporate design for lithography and manufacturability,” ASP-DAC'04: Proc. 2004 Asia and South Pacific Design Automation Conference, pp.768-773, IEEE Press, 2004.

2. [2] Taiwan Semiconductor Manufacturing Company (TSMC), Reference Flow 8.0.

3. [3] J.G. Xi, “Improving yield in rtl-to-gdsii flows,” EE Times, July 2005.

4. [4] G. Xu, L.D. Huang, D.Z. Pan, and M.D.F. Wong, “Redundant-via enhanced maze routing for yield improvement,” ASP-DAC'05: Proc. 2005 Asia and South Pacific Design Automation Conference, pp.1148-1151, ACM, 2005.

5. [5] H. Yao, Y. Cai, X. Hong, and Q. Zhou, “Improved multilevel routing with redundant via placement for yield and reliability,” GLSVLSI'05: Proc. 15th ACM Great Lakes Symposium on VLSI, pp.143-146, ACM, 2005.

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