High Performance NAND Flash Memory System with a Data Buffer-Reference-Cited by-同舟云学术

High Performance NAND Flash Memory System with a Data Buffer

Published:2013 Issue:12 Volume:E96.A Page:2645-2651
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

LEE Jung-Hoon¹,JUNG Bo-Sung¹

Affiliation:

1. Department of Electrical and Electronic Engineering (ERI), GyeongSang National University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/12/E96.A_2645/_pdf

Reference20 articles.

1. [1] J. Park, S. Park, C.C. Weems, and S. Kim, “A hybrid flash translation layer for SLC-MLC flash memory based multibank solid state disk,” Microprocessors and Microsystems, vol.35, no.1, pp.48-59, Feb. 2011.

2. [2] Igor Stievano, “Flash memories,” InTech, 2011, ISBN 978-953-307-272-2.

3. [3] Toshiba, “NAND vs. NOR flash memory technology overview,” http://umcs.maine.edu/cmeadow/courses/cos335/Toshiba/20NAND_vs_NOR_Flash_Memory_Technology_Overviewt.pdf, accessed Aug. 5. 2009.

4. [4] Samsung Elec., NAND Flash Memory & Smart Media Data Book, 2010.

5. [5] M. Santarini, “NAND versus NOR,” 2005, Available from: http://www.edn.com/contents/images/6262540.pdf

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Energy-Scalable 4KB LDPC Decoding Architecture for NAND-Flash-Based Storage Systems;IEICE Transactions on Electronics;2016