Performance Enhancement in Multi Gate Tunneling Field Effect Transistors by Scaling the Fin-Width-Reference-Cited by-同舟云学术

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Performance Enhancement in Multi Gate Tunneling Field Effect Transistors by Scaling the Fin-Width

Published:2010-04-20 Issue:4 Volume:49 Page:04DC10
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:en
Short-container-title:Jpn. J. Appl. Phys.

Author:

Leonelli Daniele,Vandooren Anne,Rooyackers Rita,Verhulst Anne S.,Gendt Stefan De,Heyns Marc M.,Groeseneken Guido

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Reference15 articles.

1. Silicon surface tunnel transistor

2. First demonstration of a planar-type surface tunnel transistor (STT): Lateral interband tunnel device

3. Tunnel charge transport within silicon in reversely-biased MOS tunnel structures

4. Comparing Carbon Nanotube Transistors—The Ideal Choice: A Novel Tunneling Device Design

5. Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization

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