Sidewall Dislocations in Embedded SiGe Source/Drain Areas of MOSFETs and Their Impact on the Device Performance-Reference-Cited by-同舟云学术

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Sidewall Dislocations in Embedded SiGe Source/Drain Areas of MOSFETs and Their Impact on the Device Performance

Published:2006-10-20 Issue:7 Volume:3 Page:713-718
ISSN:1938-5862
Container-title:ECS Transactions
language:
Short-container-title:ECS Trans.

Author:

Kammler Thorsten,Peidous Igor,Wei Andy,Reichel Carsten,Heinemann Stefan,Romero Karla,Engelmann Hans-Juergen

Abstract

Strain-engineered PMOS devices have been characterized by physical and electrical analysis, and computer modeling. Characteristic defects at the sidewall of embedded SiGe were found to degrade transistor performance. This could be attributed to carrier scattering rather than stress relaxation.

Publisher

The Electrochemical Society

Link

https://iopscience.iop.org/article/10.1149/1.2355866/pdf

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Facet engineering for SiGe/Si stressors in advanced CMOS technology;Solid-State Electronics;2015-08

2. Effects of patterning induced stress relaxation in strained SOI/SiGe layers and substrate;Journal of Applied Physics;2011-06-15

3. Enhancing epitaxial SixC1−x deposition by adding Ge;Thin Solid Films;2010-03

4. SiGe channels for higher mobility CMOS devices;MRS Proceedings;2009

5. Novel enhanced stressors with graded encapsulated SiGe embedded in the source and drain areas;Materials Science and Engineering: B;2008-12

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