Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration-Reference-Cited by-同舟云学术

Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

Published:2019 Issue:8 Volume:8 Page:P392-P399
ISSN:2162-8769
Container-title:ECS Journal of Solid State Science and Technology
language:en
Short-container-title:ECS J. Solid State Sci. Technol.

Author:

Porret C.^ORCID,Hikavyy A.,Granados J. F. Gomez,Baudot S.,Vohra A.^ORCID,Kunert B.,Douhard B.,Bogdanowicz J.,Schaekers M.,Kohen D.,Margetis J.,Tolle J.,Lima L. P. B.,Sammak A.,Scappucci G.,Rosseel E.,Langer R.,Loo R.^ORCID

Publisher

The Electrochemical Society

Subject

Electronic, Optical and Magnetic Materials

Reference42 articles.

1. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors

2. A comparative study of strain and Ge content in Si1−xGex channel using planar FETs, FinFETs, and strained relaxed buffer layer FinFETs

3. Gate-all-around MOSFETs based on vertically stacked horizontal Si nanowires in a replacement metal gate process on bulk Si substrates

4. Si-cap-free SiGe p-channel FinFETs and gate-all-around transistors in a replacement metal gate process: Interface trap density reduction and performance improvement by high-pressure deuterium anneal

5. Processing Technologies for Advanced Ge Devices

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