Trap-Assisted Tunneling in Deep-Submicron Ge pFET Junctions

Abstract

This work focuses on the analytical description of junction leakage in the low-voltage range (<1V) of short-channel HDD junctions, where the dominant contribution comes from the TAT regime. Starting from diodes with varying area/perimeter ratios, the area leakage contribution to the total junction leakage is experimentally determined for junctions with varying halo conditions and threading dislocation density (TDD). On the other hand, the Synopsys software of Sentaurus-Process and MEDICI was used to verify the electrical models.