(Invited) Modeling Extended Defects in Semiconductor Devices

Abstract

The most widely used in the industry stress engineering technique is based on introducing crystal lattice mismatch stress by growing SiGe on Si. For the power switches, GaN is epitaxially grown on an AlGaN buffer on top of Si wafer. The lattice mismatch stress can be high enough to introduce edge dislocations and stacking faults. We perform analysis of several key aspects of the extended defect formation and their impact on silicon and GaN transistors. We demonstrate modeling methodology to determine where a stacking fault is going to move driven by a stress gradient. Once a dislocation has found its energetically favorable location, it can be either inside or outside of the area sensitive to transistor performance. We explore the impact of a dislocation on the carrier scattering for the on-state current of advanced Si CMOS transistors and the impact of threading dislocations on power GaN switches.