Equivalent Circuit for NBTI Evaluation in CMOS Logic Gates

Abstract

As technology scales, effects such as NBTI increase their importance. The performance degradation in CMOS circuits caused by NBTI is being studied for many years and several models are available. In this work, an equivalent circuit representing one of these models is presented and evaluated through electrical simulation. The proposed circuit is process independent once the chosen model does not present any relation to technology parameters. Experimental results indicate that the equivalent circuit is valid to evaluate the degradation of PMOS transistors due to aging. Using the proposed circuit, threshold voltage degradation of each transistor may be simulated individually, which allows the evaluation of complex CMOS gates in a linear cost in relation to the number of transistors.