(Invited) Challenges in Fabricating and Scaling up Silicon Carbide Wafers and Devices

Abstract

Silicon Carbide is rapidly growing in the power electronics industry. This is fueled to a great degree by the adoption of electric cars and power electronics needed both inside the vehicle and to support the charging infrastructure. This attention from automotive industry comes with a clear spotlight on the cost, quality, and efficiency of SiC power devices. This in turn results in intense pressure and scrutiny to improve yields and reduce defects in every part of the manufacturing chain. There is a wide release and proliferation of Diode and MOSFET devices from various companies in the marketplace. Several companies are investing billions of dollars in capacity expansions driving exponential growth of wafers and devices. In this review, we will discuss the steps and processes of fabricating a SiC wafer including crystal growth, wafering, epitaxy and device fabrication. The process challenges associated with the steps unique to SiC will be highlighted with a perspective on scaling up volumes and the transition to 200mm wafers. New innovations at some of the steps are enabling higher efficiency and output. The impact of these innovations will be presented. In addition, defects at each step of the process will be reviewed along with how they interact with the following steps [1]. Finally, the effect of various processes and defects on devices and reliability will be presented [2,3]. References: H. Das, et. al., Mater. Sci. Forum, Vol. 1004, pp 458-463, (2020) T. Neyer et. al., 2021 IEEE International Reliability Physics Symposium (IRPS), pp. 1-6, (2021) S. Kochoska et. al., Mater. Sci. Forum, Vol. 1062, pp 554-559, (2022)