Charge Trapping Effects in High-k Transistors

Abstract

Fast transient and relatively slow constant voltage stress (CVS) electron trapping phenomena in high-k gate dielectrics are investigated. It is suggested that the resonance tunneling of the injected electrons directly into the shallow defect states is responsible for the fast transient trapping, while the temperature-activated electron migration between the traps govern slow CVS trapping. The extracted trap energies and their effective dimensions fit the calculated characteristics of the O vacancies in monoclinic hafnia. The relationship between trap characteristics and the reduction of trapping observed in ultra- thin high-k gate stacks is discussed.