New Method for Identifying Yield Impacting Polishing Induced Defects (PID) on Polished Silicon Substrates

Abstract

This paper talks about a new class of yield impacting defect types known as polishing induced defects (PID) on polished silicon substrates. These defects were found to cause significant yield drop associated with a pump bias failure in the sub-60nm flash memory process. Traditional incoming wafer quality analysis methods proved inadequate in detecting these defects. Nor had the problem been detected during outgoing wafer quality analysis at the wafer manufacturing plant. At the fab, SEM and AFM were able to verify the defect issue as PID; however, neither of these techniques is production-worthy for routine inspection of incoming wafers. This called for a new non-destructive methodology that not only enables capturing these defects but also provides an ability to reliably distinguish between these device-killing defects and innocuous particles which can be cleanable. This study utilized KLA-Tencor's Surfscan SP2XP unpatterned wafer inspection system, a tool with unique technology to combine multiple illumination angles and multiple detectors with a Rule Based Binning (RBB) algorithm for effective defect detection and classification. Three different rules were developed to improve the classification of PID vs. particles. All three were based on comparing the ratio of scattering signals between detectors or combinations of detectors