Design of a Fast Chirp PLL Using Digital Phase Interpolator
Author:
Funder
Samsung
Publisher
Korean Institute of Electromagnetic Engineering and Science
Link
http://jkiees.org/download/download_pdf?doi=10.5515/KJKIEES.2024.35.3.239
Reference8 articles.
1. H. Jiang, Z. Zhang, Z. Shen, X. Hao, Z. Liu, and H. Li, et al., "A calibration-free fractional-N ADPLL usibg retiming architecture and a 9-bit 0.3ps-INL phase interpolator," in IEEE Internatinal Symposium on Circuit and Systems(ISCAS), Sapporo, May 2019, pp. 1-5. 10.1109/ISCAS.2019.8702316
2. P. T. Renukaswamy, N. Markulic, P. Wambacq, and J. Craninckx, "A 12 mW 10-GHz FMCW PLL based on an integrating DAC with 28-kHz RMS frequency-error for 23-MHz/μs slope and 1.2-GHz chirp-bandwidth," IEEE Journal of Solid-State Circuit, vol. 55, no. 12, pp. 3294-3307 Dec. 2020. 10.1109/JSSC.2020.3021311
3. Y. S. Jeon, J. H. Moon, S. J. Park, J. U. Shin, and B. S. Kim, "Design of a fast chirp frequency synthesizer using 28-nm CMOS process," The Journal of Korean Institute of Electromagnetic Engineering and Science, vol. 32, no. 10, pp. 303-309, Apr. 2023. 10.5515/KJKIEES.2023.34.4.303
4. Q. Shi, K. Bunsen, N. Markulic, and J. Craninckx, "A self-calibrated 16-GHz subsampling-PLL-based fast-chirp FMCW modulator with 1.5-GHz bandwidth," IEEE Journal of Solid-State Circuits, vol. 54, no. 12, pp. 3503-3512, Dec. 2019. 10.1109/JSSC.2019.2941113
5. B. P. Ginsburg, K. Subburaj, S. Samala, K. Ramasubramanian, J. Singh, and S. Bhatara, et al., "A multimode 76-to-81 GHz automotive radar transceiver with autonomous monitoring," in 2018 IEEE International Solid-State Circuits Conference(ISSCC), San Francisco, CA, Feb. 2018, pp. 158-160. 10.1109/ISSCC.2018.8310232
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