Design and FPGA Implementation of Signal Strength Measurement Techniques for Satellite Communication Systems

Abstract

Communication receivers perform three major functions, frequency down conversion, IF demodulation and subcarrier demodulation. The functioning of a receiver is mainly controlled by input signal strength and relative dynamics. Signal strength is measured in terms of Signal to Noise ratio (SNR) and Carrier to Noise power density (C/No). Any measure of signal strength indirectly gives information about receiver performance for that period. Apart from this, SNR measurement in close loop with Phase Locked Loop (PLL) parameter forms the adaptive PLL system, which is one of the driving forces for this paper. The focus of this paper is to find suitable signal strength measurement techniques and their implementation for satellite communication systems. Signal to Noise Variance method (SNV) and Narrow band Wide band Power Ratio (NWPR) methods are considered based on the performance and realization aspects. All techniques require division, logarithm, and multiplication functions for their realization in hardware. CO-ordinate Rotation Digital Computer (CORDIC) algorithm is considered for realizing logarithm function. A comparison study is done for developed algorithm with Intellectual Property (IP) core. Developed SNR techniques are simulated for Binary Phase Shift Keying (BPSK) demodulator system and performance is evaluated for Additive White Gaussian Noise (AWGN). The paper describes the FPGA design and simulations of these techniques. Developed design is targeted to commercial and space qualified FPGA platforms. FPGA implementations results are compared with system level simulation results, and both are found to be satisfactory. Application of developed system in adaptive BPSK demodulator is also presented.