Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme-Reference-Cited by-同舟云学术

Power-efficient dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme

Published:2016-09 Issue:9 Volume:17 Page:962-972
ISSN:2095-9184
Container-title:Frontiers of Information Technology & Electronic Engineering
language:en
Short-container-title:Frontiers Inf Technol Electronic Eng

Author:

Geng Liang,Shen Ji-zhong,Xu Cong-yuan

Publisher

Zhejiang University Press

Subject

Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/article/10.1631/FITEE.1500293/fulltext.html

Reference25 articles.

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2. Goh, W.L., Yeo, K.S., Zhang, W., et al., 2007. A novel static dual edge-trigger flip-flop for high-frequency low-power application. IEEE Int. Symp. on Integrated Circuits, p.208–211. http://dx.doi.org/10.1109/ISICIR.2007.4441834

3. Hwang, Y.T., Lin, J.F., Sheu, M.H., 2012. Low-power pulse-triggered flip-flop design with conditional pulseenhancement scheme. IEEE Trans. VLSI Syst., 20(2): 361–366. http://dx.doi.org/10.1109/TVLSI.2010.2096483

4. Hyman, R., Ranganathan, N., Bingel, T., et al., 2013. A clock control strategy for peak power and RMS current reduction using path clustering. IEEE Trans. VLSI Syst., 21(2): 259–269. http://dx.doi.org/10.1109/TVLSI.2012.2186989

5. Judy, D.J., Kanchana Bhaaskaran, V.S., 2012. Energy recovery clock gating scheme and negative edge triggering flip-flop for low power applications. Int. Conf. on Devices, Circuits and Systems, p.140–143. http://dx.doi.org/10.1109/ICDCSyst.2012.6188691

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