Getting ready for EUV in HVM-Reference-Cited by-同舟云学术

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Getting ready for EUV in HVM

Published:2015-09-04 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
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Author:

Dicker Gerald,de Bruin Diederik,Peterson Brennan,Wöltgens Pieter,Sluijk Boudewijn,Jenkins Peter

Publisher

SPIE

Reference7 articles.

1. Cramming More Components onto Integrated Circuits;Moore,1965

2. International Roadmap for Semiconductors. http://www.itrs.net/

3. Holt, Bill., Intel Investor Meeting 2014. http://www.intc.com/presentations.cfm

4. Contact Level Patterning Challenges for Sub 22-nm Architecture;Shearer,2014

5. The daunting complexity of scaling to 7nm without EUV: pushing DTCO to the extreme;Liebmann,2015

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. ASAP5: A predictive PDK for the 5 nm node;Microelectronics Journal;2022-08

2. LWR enhancement for 300mm track processing;Advances in Patterning Materials and Processes XXXV;2018-03-13

3. ASAP7: A 7-nm finFET predictive process design kit;Microelectronics Journal;2016-07

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