Real time EPE measurement as a yield correlated metrology on advanced DRAM nodes
Author:
Publisher
SPIE
Reference8 articles.
1. Edge placement error fundamentals and impact of EUV: will traditional design-rule calculations work in the era of EUV?
2. EPE budget analysis and margin co-optimization on the multiple critical on-device features in a single image for yield enhancement;Abramovitz,2021
3. Evaluation of robust EPE monitoring and control metric methodologies for advanced DRAM nodes yield improvement
4. Budgeting and predicting pattern defects using edge placement error and machine learning
5. On device EPE: minimizing overlay, pattern placement, and pitch-walk, in presence of EUV stochastics and etch variations;Adan,2019
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