1. EUV mask readiness and challenges for the 22nm half pitch and beyond;Chan,2011
2. ASML’s NXE platform performance and volume introduction;Peeters,2013
3. Evaluation of double-patterning techniques for advanced logic nodes;Koay,2010
4. Advanced patterning solutions based on double exposure: double patterning and beyond;Bae,2009
5. Process capability comparison between LELE DPT and spacer for NAND flash 32nm and below;Tseng,2008