Litho process development for pillars to enable high density 4f2 memory cells at 34nm pitch
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SPIE
Reference5 articles.
1. High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications;Kim,2010
2. Orthogonal array pillar process development for high density 4F2 memory cells at 40nm pitch and beyond
3. Coater/Developer-Based Techniques to Achieve Tight Pitches Towards High NA EUV;Kato,2023
4. Screening of 193i and EUV lithography process options for STT-MRAM orthogonal array MTJ pillars;Pak;Micro and Nano Engineering Journal,2021
5. Evaluation of EUV resist materials for use at the 32nm half-pitch node;Wallow,2008
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