Tri-layer resist process for fabricating sub 45-nm L&S patterns by EPL-Reference-Cited by-同舟云学术

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Tri-layer resist process for fabricating sub 45-nm L&S patterns by EPL

Published:2006-03-10 Issue: Volume: Page:
ISSN:0277-786X
Container-title:SPIE Proceedings
language:
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Author:

Koba Fumihiro,Matsumaro Kazuyuki,Soda Eiichi,Watanabe Tadayoshi,Matsubara Yoshihisa,Arimoto Hiroshi,Matsumiya Tasuku,Kawana Daisuke,Yamashita Naoki,Fujii Yasushi,Ohmori Katsumi,Sato Mitsuru,Kozawa Takahiro,Tagawa Seiichi

Publisher

SPIE

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Systematic defect improvement integration of dual damascene processes development on nano semiconductor fabrication;Materials Science in Semiconductor Processing;2010-12

2. Novel Approach of Semiconductor Manufacturing Process on Copper Dual Damascene Processes Integration;Strain;2009-06

3. Optimal Integration Process for Elimination of Abnormal Striation on Wafer Dual Damascene Processes;Japanese Journal of Applied Physics;2009-04-20

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