Author:
Liebmann Lars,Pileggi Larry,Hibbeler Jason,Rovner Vyacheslav,Jhaveri Tejas,Northrop Greg
Cited by
23 articles.
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1. LEO: Line End Optimizer for Sub-7nm Technology Nodes;Proceedings of the 2022 International Symposium on Physical Design;2022-04-13
2. 芯片制造语境下的计算光刻技术;Laser & Optoelectronics Progress;2022
3. Logic IP for Low-Cost IC Design in Advanced CMOS Nodes;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-02
4. Pattern-based analytics to estimate and track yield risk of designs down to 7nm;SPIE Proceedings;2017-03-30
5. Cut Mask Optimization With Wire Planning in Self-Aligned Multiple Patterning Full-Chip Routing;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-02