Low-latency power-dividing clocking scheme for adiabatic quantum-flux-parametron logic-Reference-Cited by-同舟云学术

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Low-latency power-dividing clocking scheme for adiabatic quantum-flux-parametron logic

Published:2020-05-04 Issue:18 Volume:116 Page:182602
ISSN:0003-6951
Container-title:Applied Physics Letters
language:en
Short-container-title:Appl. Phys. Lett.

Author:

He Yuxing¹^ORCID,Takeuchi Naoki¹^ORCID,Yoshikawa Nobuyuki¹²^ORCID

Affiliation:

1. Institute of Advanced Sciences, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501, Japan

2. Department of Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501, Japan

Funder

Japan Society for the Promotion of Science

Publisher

AIP Publishing

Subject

Physics and Astronomy (miscellaneous)

Link

http://aip.scitation.org/doi/pdf/10.1063/5.0005612

Reference16 articles.

1. Energy-Efficient Superconducting Computing—Power Budgets and Requirements

2. Cryogenic Computing Complexity Program: Phase 1 Introduction

3. Superconducting Computing in Large-Scale Hybrid Systems

4. RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems

5. Energy-Efficient Single Flux Quantum Technology

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1. A bifunctional superconducting cell as flux qubit and neuron;Beilstein Journal of Nanotechnology;2023-11-21

2. Synchronization;Single Flux Quantum Integrated Circuit Design;2023-11-17

3. Results From the ColdFlux Superconductor Integrated Circuit Design Tool Project;IEEE Transactions on Applied Superconductivity;2023-11

4. SupeRBNN: Randomized Binary Neural Network Using Adiabatic Superconductor Josephson Devices;56th Annual IEEE/ACM International Symposium on Microarchitecture;2023-10-28

5. A Full-Custom Design Flow and a Top-Down RTL-to-GDS Flow for Adiabatic Quantum-Flux-Parametron Logic Using a Commercial EDA Design Suite;IEEE Transactions on Applied Superconductivity;2023-08

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