1. Y-J Chang, Yu-Cheng, Shao-Chi Liao and Chun-Hsiao, “A Low power Radix-4 booth multiplier with pre-encoded mechanism,” IEEE Access Comput, May 2020, pp. 3003684
2. G.-N. Sung, Y.-J. Ciou, and C.-C. Wang, “A power-aware 2-dimensional bypassing multiplier using cell-based design flow,” in Proc. IEEE Int. Symp. Circuits Syst., May 2008, pp. 3338–3341.
3. G.-L. Jiang, T.-C. Wu, and Y.-J. Chang, “Low power multiplier with alternative bypassing implementation,” in Proc. Int. Conf. Embedded Syst. Appl. (ESA), Jul. 2012, pp. 77–82.
4. A Modified Partial Product Generator for Redundant Binary Multipliers
5. A Two-Speed, Radix-4, Serial–Parallel Multiplier