Experimental examination of tunneling paths in SiGe/Si gate-normal tunneling field-effect transistors
Author:
Affiliation:
1. Peter Grünberg Institut (PGI-9) and JARA-FIT, Forschungszentrum Jülich GmbH, 52425 Jülich, Germany
2. Dipartimento Politecnico di Ingegneria e Architettura (DPIA), University of Udine, 33100 Udine, Italy
Funder
European Commission
Bundesministerium für Bildung und Forschung
Publisher
AIP Publishing
Subject
Physics and Astronomy (miscellaneous)
Link
http://aip.scitation.org/doi/pdf/10.1063/1.4996109
Reference21 articles.
1. Low-Voltage Tunnel Transistors for Beyond CMOS Logic
2. Tunnel field-effect transistors as energy-efficient electronic switches
3. Leakage-Reduction Design Concepts for Low-Power Vertical Tunneling Field-Effect Transistors
4. Drain voltage dependent analytical model of tunnel field-effect transistors
5. Heterojunction Vertical Band-to-Band Tunneling Transistors for Steep Subthreshold Swing and High on Current
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