Performance limits exploration of sub-5 nm monolayer germanane transistors: A first-principle quantum transport simulation

Abstract

Two-dimensional germanium is considered a promising new channel material to replace silicon owing to its lower effective mass and larger electron–hole mobility. To investigate the transport characteristics of single-layer germanane transistors with gate lengths (Lg) below 5 nm, we utilize an ab initio quantum transport methodology. It was found that the n-type germanane transistors having Lg of 3 and 5 nm satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for the on-state current (Ion), effective delay time, and power-delay products of high-performance (HP) devices. Notably, by introducing a negative capacitive (NC) dielectric layer, the p-type germanane transistor having an Lg of 5 nm is almost able to meet the ITRS demands for HP devices. Despite reducing the gate length to 2 nm through the incorporation of the NC dielectric layer, the on-state currents for both n-type and p-type still satisfy approximately 80% of the ITRS standard. Therefore, monolayer germanane presents promising potential as a channel material in a sub-5 nm scale for HP applications.