Terahertz slow-wave scalable interconnect based on back-end-of-line (BEOL) in 40 nm CMOS

Abstract

This paper proposes a terahertz (THz) slow-wave scalable interconnect based on multilayered back-end-of-lines in a complementary metal-oxide-semi-conductor process. Capacitances are realized beside and below the signal line. The ground plane is slotted to significantly reduce the propagation velocity of electromagnetic waves and improve the quality factor. Compared with a conventional microstrip line, the proposed slow-wave interconnect not only realizes a slow-wave factor up to 1.96 but also achieves a quality factor higher than 20 at 0.14–0.15 THz. In addition, a one-step data processing method is proposed to directly calculate the performance metrics of interconnects by using the measured S-parameters of device-under-test and the Thru calibration kit. For millimeter-wave and THz chips, the proposed slow-wave interconnect is a promising candidate to realize on-chip passive components with increased quality factor as well as reduced footprint and loss.