Gate electrostatic controllability enhancement in nanotube gate all around field effect transistor

Abstract

Recently, short channel effects (SCE) and power consumption dissipation problems impose tremendous challenges that need imperative actions to be taken to deal with for field effect transistor to further scale down as semiconductor technology enters into sub-10 nm technology node. From 3 nm technology node and beyond, gate all around field effect transistor steps onto the history stage attributed to its improved SCE suppressing ability thanks to surrounding gate structure. Herein, we demonstrate the super electrostatic control ability of a double-gated nanotube gate all around field effect transistor (DG NT GAAFET) in comparison with nanotube (NT GAAFET) and nanowire gate all around field effect transistor (NW GAAFET) with the same device parameters designed. Ion boosts of 62% and 57% have been obtained in DG NT GAAFET in comparison with those of NT GAAFET and NW GAAFET. In addition, substantially suppressed SCEs have been obtained in DG NT GAAFET due to enhanced electrostatic control, which are certificated by improved Ioff, subthreshold swing (SS), and Ion/Ioff ratio obtained. On the other hand, the Ion of NT GAAFET is comparable with that of NW GAA-FET. Whereas its Ioff is 1 order smaller, SS is almost two times smaller compared with those of NW GAA-FET, manifesting the meliority of nanotube channel structure. In the end, the robustness of nanotube channel structure, especially double gated one, against channel length (Lg) scaling has been verified with Technology Computer Aided Design (TCAD) simulation study.