Effective InAsP dislocation filtering layers for InP heteroepitaxy on CMOS-standard (001) silicon

Abstract

In this work, we report InAsP-based dislocation filter layers (DFLs) for InP heteroepitaxy on CMOS-standard (001) Si substrates, demonstrating a threading dislocation density of 3.7 × 107 cm−2. The strain introduced by InAsP induces dislocation bending at the InAsP/InP interface, thereby facilitating the reaction and annihilation of dislocations during their lateral glide. Concurrently, the InP spacer exhibits tensile strain, leading to the formation of stacking faults (SFs). With a comprehensive analysis utilizing x-ray diffraction, electron channeling contrast imaging, and transmission electron microscopy, the effects of DFL-induced strain on dislocations and SFs are investigated. Fine-tuning the strain conditions allowed low-dislocation-density while SF-suppressed, anti-phase boundary free InP on Si. This work, therefore, provides a useful buffer engineering scheme for monolithic integration of InP-based electronic and photonic devices onto the industry-standard silicon platform.